Micrel
MICRF405
April 2006
24
M9999-041906
(408) 955-1690
Charge Pump and PLL Filter
Adr
Data
A6..A0
D7
D6
D5
D4
D3
D2
D1
D0
0010011 INT_LF_EN=1
CP_CUR1=0
CP_CUR0=1 LF_RES1_4=0 LF_RES1_3=1 LF_RES1_2=0 LF_RES1_1=0 LF_RES1_0=1
0010100 LF_High_PM=1
LF_CAP1=1
LF_CAP0=1 LF_RES3_4=0 LF_RES3_3=0 LF_RES3_2=1 LF_RES3_1=0 LF_RES3_0=1
0010110 INT_LF_TEST=0
VCO_IB2=0
VCO_IB1=0
VCO_IB0=0
VCO_by=0
OUTS2=0
OUTS1=0
OUTS0=0
There are two charge pumps, one for the external
loop filter, and one for the internal filter. Both pumps
have four different output current steps controlled by
the CP_CUR[1:0] bits (refer to Table 16). The
internal loop filter is a dual path type, which needs
two charge pump currents. The different steps allow
different bandwidths for the internal filter and give
greater flexibility when choosing components for the
external filter.
An external PLL loop filter is recommended when
using FSK modulation that is applied with dividers
and closed loop modulation using the modulator. For
Open Loop modulation a combination of external
and internal loop filter is recommended. In all modes
of ASK/OOK modulation, it is only possible to use
internal PLL loop filter due to the high bandwidth
requirements.
Table 15 below shows three different loop filters, the
three first are for closed loop modulation and the last
one is for open loop modulation. The component
values are calculated with RF frequency = 915MHz,
VCO gain = 67MHz/V and charge pump current =
100uA. Other settings are also shown in Table 15.
The varactor pin capacitance of 10-12pF does not
influence on the component values for the two filters
with lowest bandwidth. For the 12kHz bandwidth
filter, a third order loop filter is calculated. The third
pole is set by R2 and臗3. Here C3 is chosen to be
12pF, the same as the varactor input pin
capacitance. C3 can therefore be skipped.
A schematic for a third order loop filter is shown in
Figure 11a. For a second order filter, C3 is not
connected and R2 is 0 &. When designing a third
order loop filter, the internal capacitance on the
VARIN pin of approximately 10-12pF must be taken
into consideration. Figure 11b shows the loop filter
configuration for the open loop VCO modulation
case.
The on-chip dual path filter is shown in Figure 11c.
The dual path loop filter has capacitance
configurable in four steps, by the LF_CAP[1:0] bits.
The ratio between C1 and C2 in Figure 11 c) sets
the phase margin of the filter. If LF_High_PM bit is
not set the phase margin is 56? if it is set the phase
margin is 69? The R1 and R3 resistor value is set
separately in 32 steps by the LF_RES1[4:0] and
LF_RES3[4:0] bits.
The on-chip dual path filter can be used when the
modulation type is set to Open-Loop VCO or ASK.
Table 18 gives the recommended settings for the
internal component values for various bitrates and
phase detector frequencies. The settings are
calculated to give optimal phase margin for the given
phase-frequency-detector frequency and loop filter
bandwidth. (More values of C and R can be found in
Table 52 and Table 52 on page 40 and 41).
CP_CUR1
CP_CUR0
External Charge Pump Current
Internal Charge Pump Current
0
0
12.5礎
1.25/12.5礎
0
1
25礎
3.125/31.25礎
1
0
50礎
6.25/62.5礎
1
1
100礎
12.5/125礎
Table 16. Charge Pump.
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